Low power buffer with open drain output, 74AUP1G07 Replace 74AUP1G07GW.
FEATURES

• Wide Supply Voltage Range: 0.8V to 3.6V

• Inputs Accept Voltages Higher than the Supply 

  Voltage

• 4mA Output Current

• Low Quiescent Current: ICC = 0.1μA (TYP)

• Low Dynamic Power Dissipation: 

  CPD = 2.5pF at VCC = 3.3V (TYP)

• Input with Schmitt-Trigger 

• Support Partial Power-Down Mode

• -40℃ to +125℃ Operating Temperature Range

• Available in Green SC70-5, SOT-23-5 and 

  UTDFN-1.45×1-6AL Packages








PIN CONFIGUTION
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74AUP1G07GW 74AUP1G07GW.pdf

No.13724

FEATURES

• Wide supply voltage range from 0.8 V to 3.6 V

• High noise immunity

• CMOS low power dissipation

• Complies with JEDEC standards:

• JESD8-12 (0.8 V to 1.3 V)

• JESD8-11 (0.9 V to 1.65 V)

• JESD8-7 (1.65 V to 1.95 V)

• JESD8-5 (2.3 V to 2.7 V)

• JESD8C (2.7 V to 3.6 V)

• ESD protection:

• HBM: ANSI/ESDA/JEDEC JS-001 Class 3A exceeds 5000 V

• CDM: ANSI/ESDA/JEDEC JS-002 Class C3 exceeds 1000 V

• MM: JESD22-A115-A exceeds 200 V

• Low static power consumption; ICC = 0.9 μA (maximum)

• Latch-up performance exceeds 100 mA per JESD 78 Class II

• Overvoltage tolerant inputs to 3.6 V

• Low noise overshoot and undershoot < 10 % of VCC

• IOFF circuitry provides partial Power-down mode operation

• Multiple package options

PIN CONFIGUTION
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