Single Schmitt trigger buffer, 74LVC1G17XN5G Replace 74LVC1G17GV.
74LVC1G17XN5G 74LVC1G17XN5G.pdf
FEATURES

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PIN CONFIGUTION
优势替代
74LVC1G17GV 74LVC1G17GV.pdf

No.13697

FEATURES

• Wide supply voltage range from 1.65 V to 5.5 V

• Overvoltage tolerant inputs to 5.5 V

• High noise immunity

• CMOS low power dissipation

• IOFF circuitry provides partial 

  Power-down mode operation

• ±24 mA output drive (VCC = 3.0 V)

• Latch-up performance exceeds 250 mA

• Direct interface with TTL levels

• Unlimited rise and fall times

• Complies with JEDEC standard:

• JESD8-7 (1.65 V to 1.95 V)

• JESD8-5 (2.3 V to 2.7 V)

• JESD8C (2.7 V to 3.6 V)

• JESD36 (4.5 V to 5.5 V)

• ESD protection:

• HBM: ANSI/ESDA/JEDEC JS-001 Class 2 exceeds 2000 V

• MM: JESD22-A115-A exceeds 200 V

• Multiple package options

• Specified from -40 °C to +85 °C and -40 °C to +125 °C.

PIN CONFIGUTION
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